Many integrated circuits currently benefit from the advantages of complimentary metal-oxide-semiconductor (CMOS) technology. CMOS circuits employ both p-type MOS (PMOS) transistors and n-type MOS (NMOS) transistors to achieve the desired circuit operation. However, utilization of PMOS transistors suffers from certain disadvantages, including increased area requirements due to the required minimum spacing between PMOS and NMOS transistors, as dictated by the semiconductor process employed. Further, reduced current driveability is due to the lower mobility of holes as compared with electrons. Some circuits, e.g., dynamic random access memory (DRAM) circuits, suffer more significantly from these disadvantages, since they require high bit density and high speed performance.
In order to avoid the problem of increased area consumption, DRAMs are often designed using only NMOS circuitry for certain portions. These portions typically include pitch-constrained portions, such as the memory cell circuitry of the DRAM, the bit-line sense amplifier circuitry, row and column decoder circuitry, and word-line driver circuitry. However, NMOS circuitry tends to suffer from an inability to output a logic "HIGH" level equal to the voltage supply level, VDD, of the circuitry. Typically, application of the voltage supply level VDD to the drain and gate terminals of an NMOS transistor produces a maximum voltage at the source terminal equal to VDD less the threshold voltage (Vt) of the transistor (e.g., VDD-Vt), as is well known to those skilled in the art.
In order to better achieve proper "HIGH" logic level output from NMOS circuitry, especially for word-line driver circuitry, some systems employ depletion-mode NMOS transistors, which have a threshold voltage less than zero volts, to avoid the reduced maximum voltage. Unfortunately, extra processing steps are typically required to produce depletion-mode NMOS transistors. Further, a negative gate voltage is needed turn the depletion-mode NMOS transistor off.
Other systems employ bootstrap circuitry to better drive the word lines in a DRAM. While differing implementations of bootstrap circuits are well known, typically only self-bootstrap circuits are suitable for use in pitch-constrained circuits, such as word-line driver circuits. An example of a typical prior art self-bootstrap circuit is presented with reference to FIG. 1. A SELECT signal from a row decoder circuit (not shown) is input at a node 10. The signal is inverted via the transistors 12 and 14, e.g., a HIGH level SELECT signal at node 10 results in a LOW level signal at node 16. The signal at node 16 is then suitably inverted via the transistors 18 and 20, e.g., the LOW level signal at node 16 results in a HIGH level signal at node 22. The transistors 12 and 18 suitably comprise PMOS transistors coupled at a source to VDD and a drain to a drain of transistor 14 or 20, respectively, where transistors 14 and 20 suitably comprise NMOS transistors, with each of their sources coupled to ground.
With a LOW level signal at node 16, transistor 24, e.g. an NMOS transistor coupled at a source to ground, at a drain to a Wordline output coupled to a row of memory cells (not shown), and at a gate to node 16, is suitably turned off. A transistor 26, e.g., an NMOS transistor coupled at a gate to VDD, at a drain to node 22 and at a source to a node 28, is turned on. The voltage at node 28, VG, goes to a level of VDD-Vt.sub.26 (VDD less the threshold voltage of transistor 26). Once the voltage VG is settled, the voltage input as a boost voltage, Vboost, to a drain of an NMOS transistor 30, is increased from a ground potential to a higher value, e.g., VDD+1.5 volts (V). Capacitive coupling suitably raises VG high enough for the signal Vboost to pass through transistor 30 without a voltage drop.
Conversely, with a LOW level SELECT signal, a HIGH level signal is present at node 16. This turns transistor 24 on, which results in the Wordline output being pulled to the ground voltage potential.
While the self-bootstrap circuit of FIG. 1 may successfully drive the Wordline output for some circuit designs, problems arise when the threshold voltages of transistors 26, 30, or in the memory cell coupled to receive the Wordline output, are too high, which lowers the voltage level of the HIGH level signal being transmitted and causes an insufficient word-line voltage. Further, as reduced power consumption in circuitry becomes more desirable, the supply voltage VDD decreases. Unfortunately, a proportional decrease in the threshold voltage of the self-bootstrap circuit's transistors is usually not achieved. Again, this results in the output of the word-line driver circuitry providing an insufficient word-line driver voltage.
Accordingly, what is needed is a self-bootstrap circuit that provides sufficient voltage levels for circuitry powered by reduced power supply voltages.